All
Search
Images
Videos
Shorts
Maps
News
More
Shopping
Flights
Travel
Notebook
Report an inappropriate content
Please select one of the options below.
Not Relevant
Offensive
Adult
Child Sexual Abuse
Length
All
Short (less than 5 minutes)
Medium (5-20 minutes)
Long (more than 20 minutes)
Date
All
Past 24 hours
Past week
Past month
Past year
Resolution
All
Lower than 360p
360p or higher
480p or higher
720p or higher
1080p or higher
Source
All
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
Price
All
Free
Paid
Clear filters
SafeSearch:
Moderate
Strict
Moderate (default)
Off
Filter
PrimeSim: Circuit Simulation Solution | Synopsys
4 weeks ago
synopsys.com
14:50
新思在线课程:统一的Debug平台Verdi - 新思科技 (Synopsys Inc.) -
…
Mar 23, 2020
synopsys.com
2:44
Automatically Generate, Budget and Optimize UPF with Synopsys Verd
…
26.2K views
May 17, 2023
YouTube
EE Journal
9:11
UVM-1: UVM Basics | Synopsys
88.4K views
Dec 21, 2015
YouTube
Synopsys
50:46
Synthesis in Synopsys Design Vision GUI tutorial
24.2K views
Sep 12, 2017
YouTube
VLSI Techno
20:49
Synopsys Tutorial Part 1 - Introduction to Synopsys Custom
…
67K views
Aug 7, 2013
YouTube
Bangonkali
5:21
What is Boundary Scan?
100.5K views
Jun 23, 2015
YouTube
TechSharpen
9:08
Unleashing SystemVerilog and UVM: Introduction | Synopsys
77.6K views
Dec 21, 2015
YouTube
Synopsys
24:15
Synopsys IC Compiler (ICC) basic tutorial
79.2K views
Feb 16, 2015
YouTube
Vivek Gupta
6:09
Interactive Reverse Debug in Verdi
16.3K views
Nov 25, 2016
YouTube
jonathan cheah
5:45
Interactive Debug with Verdi | Synopsys
72K views
Feb 1, 2018
YouTube
Synopsys
16:40
Synopsys VCS Basic tutorial - HDL simulation flow
52.4K views
Aug 16, 2017
YouTube
VLSI Techno
14:01
Installation procedure Of Synopsys Tools
28.5K views
Jul 27, 2017
YouTube
VLSI Techno
7:59
SV-1: Object-oriented Programming for Designers | Synopsys
47.9K views
Dec 21, 2015
YouTube
Synopsys
5:15
Synopsys EDA tools Installation | Synopsys tool installation demo
12.7K views
Dec 19, 2016
YouTube
Team VLSI
1:01:00
ASIC DESIGN- LOGIC SYNTHESIS & PHYSICAL DESIGN USING SYNOP
…
24.5K views
Sep 3, 2017
YouTube
Melvin Sen Thomas
1:50
Custom Compiler’s Visually-Assisted Layout Automation in Ac
…
3.5K views
Feb 25, 2020
YouTube
Synopsys
5:17
Cool Things You Can Do with Verdi – Verification Planning (Introducti
…
12.1K views
Mar 1, 2016
YouTube
Synopsys
5:32
Cool Things You Can Do with Verdi - Introduction | Synopsys
30.5K views
Jul 21, 2014
YouTube
Synopsys
28:00
SDC file | Synopsys Design Constraints file | various files in V
…
40.6K views
Jun 6, 2019
YouTube
Team VLSI
9:41
Using nCompare to Compare Waveforms in Two FSDB Files | Sy
…
18.6K views
Feb 1, 2018
YouTube
Synopsys
9:34
WinCC Unified V16: first steps with Custom Web Controls part1
26.2K views
Dec 3, 2020
YouTube
DerHecht4.0
3:53
Using Verdi for Design Understanding - Driver/Load Traci
…
16.1K views
Jul 10, 2020
YouTube
Synopsys
13:05
Custom Compiler’s Visually-Assisted Layout Automation in Ac
…
3.6K views
Apr 29, 2020
YouTube
Synopsys
2:53
CCD Everywhere throughout the RTL-to-GDSII Design Flow with Sy
…
3.5K views
Dec 4, 2019
YouTube
Synopsys
16:03
Logic Equivalence Check | Synopsys Formality Tutorial | RT
…
19.6K views
Oct 31, 2018
YouTube
Team VLSI
6:23
Focus on Active Source Code with Verdi Source Code Viewer | Synop
…
11.2K views
Feb 1, 2018
YouTube
Synopsys
11:16
Logic Synthesis of RTL | Synopsys Design Compiler | Synopsys DC |
…
39K views
Oct 28, 2018
YouTube
Team VLSI
6:40
AMS Co-simulation Debug with Verdi | Synopsys
6.8K views
Feb 1, 2018
YouTube
Synopsys
16:38
Logic Synthesis flow | RTL Synthesis flow | RTL2GDS | Desig
…
34.8K views
Oct 28, 2018
YouTube
Team VLSI
See more videos
More like this
Feedback